US20020036935A1  Programmable high speed frequency divider  Google Patents
Programmable high speed frequency divider Download PDFInfo
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 US20020036935A1 US20020036935A1 US09/950,817 US95081701A US2002036935A1 US 20020036935 A1 US20020036935 A1 US 20020036935A1 US 95081701 A US95081701 A US 95081701A US 2002036935 A1 US2002036935 A1 US 2002036935A1
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 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03K—PULSE TECHNIQUE
 H03K21/00—Details of pulse counters or frequency dividers
 H03K21/38—Starting, stopping or resetting the counter

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03K—PULSE TECHNIQUE
 H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
 H03K23/58—Gating or clocking signals not applied to all stages, i.e. asynchronous counters

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03K—PULSE TECHNIQUE
 H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
 H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
 H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
 H03K23/667—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by switching the base during a counting cycle
Abstract
A programmable high speed frequency divider, in which the construction of flipflops for forming a frequency divider which is capable of programming the dividing ratio of an input clock frequency is simplified in order to increase the operation speed of the frequency divider, is provided. By simplifying the structures of least significant bit flipflops, including the flipflop representing the least significant bit, among flipflops forming a frequency divider, the operation speed of the counter in the frequency divider is increased and the frequency limit of an input clock which can be divided is raised.
Description
 1. Field of the Invention
 The present invention relates to a frequency divider, and more particularly, to a programmable high speed frequency divider capable of programming the dividing ratio of an input clock frequency, in which the construction of flipflops for forming the frequency divider is simplified in order to increase the operation speed of the frequency divider.
 2. Description of the Related Art
 Generally, in order to generate a signal of a desired frequency by using a clock signal in an electronic circuit, a circuit for dividing a clock signal frequency by an arbitrary natural number N is needed. This circuit is referred to as a frequency divider.
 Here, N is a natural number equal to or greater than 2 and its maximum value differs depending on the number of bits in an implemented counter. Generally in a kbit counter, N is set to be a value within a range defined by the following equation 1:
 2≦N≦2 ^{k}−1 (1)
 FIG. 1 is a circuit diagram of a prior art 6bit counter which is used in a frequency divider. Because k is 6, the counter has 6 flipflops, each having a set function and a reset function.
 A clock signal which is desired to be divided is input to flipflop (FF11) representing the least significant bit. The counter has an asynchronous structure in which the output signal of a flipflop is the clock input of the next digit flipflop. When a clock signal passes through bitbybit from the least significant bit to the most significant bit, the output frequency of each flipflop decreases by half.
 When the dividing ratio of an input clock signal is set to N, flipflops (FF11FF16) forming the counter are initialized to represent N by signals st1 through st6 and rst1 through rst6 which are generated in a control circuit 10. For example, if N is 19, i.e., the binary number 010011, the six flipflops (FF11FF16) are set to represent the bits of the binary number in reverse order, i.e., the six flipflops (FF11FF16) are set to represent the bits 1, 1, 0, 0, 1, 0, respectively. To set a flipflop to ‘1’, a set signal is applied to the flipflop, and to set the flipflop to ‘0’, a reset signal is applied to the flipflop.
 Whenever a clock signal is applied to the flipflop representing the least significant bit (FF11), the number represented by the 6bit counter (FF11FF16) decreases gradually. If the number represented by the 6bit counter (FF11FF16) becomes ‘0’, N is again loaded into the flipflops of the counter by a set or reset signal, and counting is carried out in the decreasing direction.
 When N is loaded, a signal having a predetermined cycle is generated by the control circuit10 of the counter. The generated frequency of this signal is the value obtained by dividing an input clock signal frequency by N.
 FIG. 2 is a logic circuit diagram of the control circuit10 for generating a set signal and a reset signal for loading N to flipflops (FF11FF16) of the counter shown in FIG. 1.
 As shown in FIG. 2, the control circuit10 includes one flipflop (FF17) and a plurality of NAND gates (G13 and G14) and NOR gates (G11G15). The function of a circuit formed by the NAND gates and NOR gates is receiving the outputs of the six flipflops (FF11FF16) and determining whether or not the value represented by the counter and taken from the flipflop representing the most significant bit to the flipflop representing the least significant bit of the counter is ‘000010’. If the counter represents ‘000010’, the circuit provides ‘1’ to the D input terminal of flipflop FF17, and if not, the circuit provides ‘0’.
 The output of flipflop FF17 is fed back to NAND gate G14 in order to avoid providing an incorrect logical value to flipflop FF17 due to delay time by a logic circuit. Then, using the output signal of flipflop FF17, the control circuit 10 generates set signals and reset signals for the respective flipflops (FF11FF16) forming the counter. For example, when a noninverted output of flipflop FF17 is ‘1’, if a value to be loaded in an arbitrary flipflop of the counter is ‘1’, ‘1’ is provided as a set signal for the flipflop and ‘0’ is provided as a reset signal for the flipflop. However, if a value to be loaded in an arbitrary flipflop of the counter is ‘0’, ‘0’ is provided as a set signal for the flipflop and ‘1’ is provided as a reset signal for the flipflop.
 In this way, in the counter used in a frequency divider, flipflop FF11, which is located in the least significant bit among six flipflops, operates at the highest frequency, and as the signal passes through the flipflops to the flipflop in the most significant bit, the maximum operating frequency decreases by half at each flipflop. Therefore, flipflops operating at higher frequencies must have simpler structures so they can operate at high speed.
 However, according to the structure of a prior art counter used in a frequency divider, all flipflops, including the flipflop representing the least significant bit, are loaded with a desired dividing ratio using set signals and reset signals. As a result, the structure of the flipflop representing the least significant bit is complex, the operating speed is relatively low, and therefore it is difficult to divide a clock signal with a higher frequency.
 To solve the abovedescribed problems, it is an objective of the present invention to provide a programmable high speed frequency divider, in which for flipflop representing the least significant bit among flipflops forming a counter, the flipflop having a simple structure, which does not use a set signal and a reset signal, is used in order to increase the operating speed of the frequency divider.
 To accomplish the objective of the present invention, there is provided a programmable high speed frequency divider having a counter in which a clock signal desired to be divided is applied to the clock terminal of the first flipflop representing the least significant bit; the output terminal of the flipflop representing the least significant bit is connected to the clock terminal of the second flipflop representing the next least significant bit, and the next flipflops are connected in the same manner through to the highest effective digit flipflop; the set terminal and reset terminal of the first flipflop are open and a logical operation result of control signals and output signals of the flipflops is applied to the input terminal of the first flipflop; and all the flipflops except the first flipflop are initialized with cycles corresponding to a dividing ratio by set signals or reset signals; and a control circuit which receives the outputs of the flipflops forming the counter, generates control signals corresponding to counting values of the counter with a predetermined logic gate circuit, and generates set signals and reset signals for initializing flipflops forming the counter with cycles corresponding to the dividing ratio.
 The above objects and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which:
 FIG. 1 is a schematic diagram of a prior art programmable frequency divider;
 FIG. 2 is a logic circuit diagram of the control circuit for loading a set signal and a reset signal into flipflops of the counter shown in FIG. 1;
 FIG. 3 is a schematic diagram of a preferred embodiment of a programmable high speed frequency divider according to the present invention;
 FIGS. 4A through 4H are schematic diagrams of logic circuits for generating a variety of control signals in the control circuit shown in FIG. 3 and for generating set and reset signals for flipflops forming the counter shown in FIG. 3; and
 FIGS. 5A through 5K are timing diagrams of the variety of control signals, and set and reset signals of flipflops shown in FIGS. 3 and 4.
 For convenience of explanation, it is assumed that a 6bit downcounter having 6 flipflops is used in a preferred embodiment of the present invention.
 As shown in FIG. 3, a programmable high speed frequency divider according to the present invention includes a counter and a control circuit20. The counter is formed with 6 flipflops (FF21FF26) and a NAND gate (G21).
 A clock signal which is desired to be divided is input to a flipflop (FF21) representing the least significant bit. The counter has an asynchronous structure in which the output signal of a flipflop is the clock input of flipflop representing the next higher bit. When a clock signal progressively passes bitbybit from the least significant bit to the most significant bit, the output frequency of each flipflop decreases by half.
 Except the flipflop (FF21) representing the least significant bit, each flipflop (FF22FF26) has a structure in which a noninverted output of the flipflop is fed back to the D input terminal of the flipflop and an inverted output of the flipflop is provided to the control circuit 20. A signal output from a NAND gate G21 to which {overscore (MX1S)} generated in the control circuit 20 and an inverted output signal of the flipflop (FF21) representing the least significant bit are input, is input to the D input terminal of the flipflop (FF21).
 In the control circuit20, the logic circuits of FIGS. 4A through 4H generate set signals (st2 and st3) for flipflop representing the second least significant bit and flipflop representing the third least significant bit (FF22 and FF23), set signals (st4, st5, and st6) and reset signals (rst4, rst5, and rst6) for flipflops (FF24FF26), and a variety control signals (PT, PTff, Y, and MX1S).
 Referring to the logic circuits of FIGS. 4A through 4H and FIGS. 5A through 5K, the generation of a variety of control signals, set signals and reset signals will now be explained.
 In FIG. 4F, if n4, n5, or n6 is input to NOR gate G28 instead of n2, the output is ST4, ST5, or ST6, respectively, instead of ST2. In FIG. 4H, if n5 or n6 is input to NAND gate G30 instead of n4, the output is RST5 or RST6, respectively, instead of RST4.
 Here, when N, the divisor of frequency division, is expressed as a binary number, n1, n2, n3, n4, n5, and n6, each of which is a binary ‘1’ and ‘0’, represent the binary number from the least significant bit to the most significant bit.
 FIGS. 5A through 5K are timing diagrams in previous stages3, 2, 1, 0, and N−1 of a clock signal (CLK), the outputs Q1, Q2, and Q3 of flipflops (FF21, FF22, and FF23), and a variety of control signals. In stage 0, an initial value (N) is loaded into the flipflops of the counter when a clock signal is provided.
 As shown in the timing diagrams, in stage0, flipflops FF21, FF22, and FF23 are initialized with values corresponding to the lowest 3 bits of N (n1, n2, and n3) by the logic circuits of FIGS. 4A through 4H, and the values Q1, Q2, and Q3 are determined. Then, as a clock signal is applied in stage N−1, downcounting is sequentially carried out.
 This process will now be explained in more detail. First, the signal PT, which is a control signal, is designed so as to convert ‘0’ to ‘1’ when the value represented by the counter and taken from the most significant bit to the least significant bit is ‘0000X0’. Then, as shown in FIG. 4D, since the inverted output of flipflop FF29 is the signal PTff and the reset input of flipflop FF29 is the signal PT, PTff becomes ‘1’ after a predetermined time. If N is an odd number, i.e., n1 is ‘1’, MX1S becomes ‘1’ by the logic circuit of FIG. 4A, and if N is an even number, i.e., n1 is ‘0’, MX1S remains as ‘0’.
 If PTff value is determined, signal values of ST2, ST4, ST5, ST6, RST4, RST5, and RST6 are determined depending on n2, n4, n5, and n6, by the logic circuits of FIGS. 4F through 4H.
 For example, if PTff is ‘1’ and n2, n4, n5, and n6 are binary ‘1010’, ST2 is ‘1’, ST4 is ‘0’, ST5 is ‘1’, ST6 is ‘0’, RST4 is ‘1’, RST5 is ‘0’, and RST6 is ‘1’. As for ST3, if Q3 is set in an interval of stage 2, an interval in which the signal PT remains ‘1’ may be shorter than one cycle and, therefore, ST3 is set by a different method. That is, as in the logic circuit of FIG. 4G, in order to make ST3 ‘1’, Q1, PTff and n3 should be ‘1’.
 In order to make the flipflop FF21 representing the least significant bit remain ‘1’ without generating a set signal, NAND gate G21 is placed on a path where the output of flipflop FF21 is fed back as an input. By using the inverted signal of the signal MX1S as an input signal of NAND gate G21, the flipflop FF21 is implemented by a flipflop having the simplest structure.
 In stage1, if MX1S is ‘1’, ‘1’ can be fed back instead of ‘0’ where ‘0’ is fed back, and therefore the flipflop FF21 can be set.
 Due to delays in the control logic circuits of FIGS. 4A through 4H, PT may be ‘1’ again in stage0 after PT becomes ‘1’ in stage 2, and ‘0’ in stage 1.
 This is because 3 most significant bits (Q4Q6) as well as Q1 and Q3 should be used to determine PT, and it takes a time to determine whether PT becomes ‘1’ or ‘0’ by using 3 most significant bits. Though Q1 is ‘1’ in stage 1 and PT temporarily becomes ‘0’, unless it is known by stage 0 that the most significant bits are still all ‘0’ or any one of the most significant bits is ‘1’, PT can be ‘1’ again if Q1 is ‘0’ in stage 0, though all the most significant bits are not ‘0’.
 A logic circuit for preventing PT errors by using the signal Y generated by the logic circuit of FIG. 4E in order to avoid the occurrence of the abovedescribed wrong determination is shown in FIG. 4C. Since the signal Y is unconditionally ‘0’ in stage1 and stage 0 if N is a number equal to or greater than 8, PT unconditionally becomes ‘0’. However, if N is a number equal to or less than 7, not any of Q4, Q5, and Q6 is set to ‘1’. Accordingly, wrong determination of PT due to delays in the logic circuits described above does not occur and at this time Y is maintained at ‘1’. Y should be ‘0’ in an interval where PT is ‘0’, Y should be ‘0’ only when N is equal to or greater than 8, and the intervals should be stage 1 and stage 0. To satisfy these three conditions, a signal X is generated by the logic circuit of FIG. 4B. Signal X is a signal which is ‘1’ when Q4, Q5, and Q6 are all ‘0’, and is ‘0’ when PTff is ‘1’.
 As this, the simplest flipflop having no set and reset signals is used for flipflop representing the least significant bit, which operates at the fastest speed among flipflops forming the counter in the frequency divider. Flipflops, each having only a set signal, are used for flipflops representing the next two bits. By making these flipflops have simpler structures than flipflops representing the most significant bits, which have both set and reset signals, the overall operation speed is increased.
 The frequency divider according to the present invention has recorded a speed which is approximately 1.83 times faster than a prior art frequency divider in a simulation after layingout using HSPICE.
 According to the present invention as described above, by simplifying the structures of flipflops representing the least significant bits, including the flipflop representing the least significant bit, among flipflops forming a frequency divider, the operating speed of the counter is increased and the frequency limit of an input clock which can be divided is raised.
 Optimum embodiments have been explained in the drawings and specification, and though specific terminologies are used here, they are only used to explain the present invention. Therefore, the present invention is not restricted to the abovedescribed embodiments and many variations are possible within the spirit and scope of the present invention. The scope of the present invention is not determined by the description but by the accompanying claims.
Claims (6)
1. A programmable high speed frequency divider comprising:
a counter in which a clock signal desired to be divided is applied to the clock terminal of the first flipflop representing the least significant bit; the output terminal of the flipflop representing the least significant bit is connected to the clock terminal of the second flipflop representing the next least significant bit, and the next flipflops are connected in the same manner through to the highest effective digit flipflop; the set terminal and reset terminal of the first flipflop are open and a logical operation result of control signals and output signals of the flipflops is applied to the input terminal of the first flipflop; and all the flipflops except the first flipflop are initialized with cycles corresponding to a dividing ratio by set signals or reset signals; and
a control circuit which receives the outputs of the flipflops forming the counter, generates control signals corresponding to counting values of the counter with a predetermined logic gate circuit, and generates set signals and reset signals for initializing flipflops forming the counter with cycles corresponding to the dividing ratio.
2. The programmable high speed frequency divider of claim 1 , wherein the second and third flipflops representing the second and third least significant bits among flipflops forming the counter have open reset terminals and are initialized by set signals applied to their set terminals.
3. The programmable high speed frequency divider of claim 1 , wherein flipflops forming the counter are D flipflops.
4. The programmable high speed frequency divider of claim 1 , wherein the first flipflop has a structure in which a clock signal desired to be divided is applied to the clock terminal of the flipflop; the least significant bit (n1) of the frequency divisor (N), which is expressed as a binary number, and a control signal Y, which is set to ‘0’ in an interval where the counting value of the counter is equal to or less than ‘1’, are input to the first NAND gate; the output of the first NAND gate, the output of the first (FF1), and the output of the third flipflop (FF3) are input to a NOR gate; a signal from the output terminal of a D flipflip (its D input terminal is set to ‘1’ and a clock signal desired to be divided is input to its clock terminal) which is reset by the output signal of the NOR gate and a signal from the output terminal of the first flipflop are input to the second NAND gate; and the output of the second NAND gate is applied to the D input terminal of the first flipflop.
5. The programmable high speed frequency divider of claim 1 , wherein the second flipflop has a structure in which the output signal of the first flipflop is applied to the clock terminal of the second flipflop; a signal from the output terminal of the second flipflop is fed back to the D input terminal of the second flipflop; a signal from the output terminal of a D flipflop (its D input terminal is set to ‘1’ and a clock signal desired to be divided is input to its clock terminal) which is reset by a control signal which is ‘1’ if the outputs of the flipflops forming the counter, except the second flipflop, are all ‘0s’, and the inverted value of the second least significant bit (n2) of the frequency divisor (N), which is expressed as a binary number, are input to a NOR gate; and the output of the NOR gate is applied to the set terminal of the second flipflop.
6. The programmable high speed frequency divider of claim 1 , wherein the third flipflop has a structure in which the output signal of the second flipflop is applied to the clock terminal of the third flipflop; a signal from the output terminal of the third flipflop is fed back to the D input terminal of the third flipflop; a signal from the output terminal of a D flipflop (its D input terminal is set to ‘1’ and a clock signal desired to be divided is input to its clock terminal) which is reset by a control signal which is ‘1’ if the outputs of the flipflops forming the counter, except the second flipflop, are all ‘0s’, the inverted value of the third bit (n3) of the frequency divisor (N), which is expressed as a binary number, and a signal from the output terminal of the first flipflop are input to a NOR gate; and the output of the NOR gate is applied to the set terminal of the third flipflop.
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KR1020000012842A KR100355302B1 (en)  20000314  20000314  Programmable frequency divider by high speed counter 
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Cited By (2)
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US20060251148A1 (en) *  20030228  20061109  Welborn Matthew L  System and method for transmitting ultrawide bandwidth signals 
US8471607B1 (en)  20111230  20130625  StEricsson Sa  Highspeed frequency divider architecture 
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CN100342651C (en) *  20010829  20071010  皇家飞利浦电子股份有限公司  Frequency divider with reduced jitter and transmitter based thereon 
US7292488B2 (en) *  20050706  20071106  Infineon Technologies Ag  Temperature dependent selfrefresh module for a memory device 
JP4905354B2 (en) *  20050920  20120328  富士通株式会社  Power supply voltage adjustment device 
KR100954839B1 (en) *  20071009  20100428  고려대학교 산학협력단  Programmable Divider and method of controlling the same 
JP2010130283A (en) *  20081127  20100610  Mitsumi Electric Co Ltd  Counter circuit 
CN102118158A (en) *  20091231  20110706  中国科学院微电子研究所  Digital frequency divider with programmable highspeed broadband 
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US3774056A (en) *  19710429  19731120  Design And Manuf Corp  Digital electronic control circuit for cyclically operable appliances and the like 
JPS6144415B2 (en) *  19780818  19861002  Mitsubishi Electric Corp  
US4296380A (en) *  19790521  19811020  Matsushita Electric Industrial Co.  Programmable digital frequency divider for synthesizing signals at desired frequency 
US4741004A (en) *  19860929  19880426  Microwave Semiconductor Corporation  Highspeed programmable dividebyN counter 

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Cited By (3)
Publication number  Priority date  Publication date  Assignee  Title 

US20060251148A1 (en) *  20030228  20061109  Welborn Matthew L  System and method for transmitting ultrawide bandwidth signals 
US7570712B2 (en) *  20030228  20090804  Freescale Semiconductor, Inc.  System and method for transmitting ultrawide bandwidth signals 
US8471607B1 (en)  20111230  20130625  StEricsson Sa  Highspeed frequency divider architecture 
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US6504407B2 (en)  20030107 
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